1. Technical Field of the Invention
The present invention relates to semiconductor devices. More particularly, the present invention relates to semiconductor devices comprising a 2-DEG layer only at locations different from locations where a gate electrode is located, e.g. an enhancement mode device, i.e. a normally-off device, in which no current can flow between source and drain contact unless a positive voltage is applied to the gate electrode, and to a method for forming such semiconductor devices.
2. Description of the Related Technology
Group III-nitride devices, such as e.g. high electron mobility transistors (HEMT), comprise a two-dimensional electron gas (2 DEG) between two active layers, e.g. between a GaN layer and an AlGaN layer. This 2DEG layer is a result of piezoelectric and spontaneous polarization leading to charge separation within the materials. In known devices of this type, the 2DEG is present at zero gate bias due to the characteristics of the materials. GaN field effect transistor devices (FET) with contacts formed on top of an AlGaN layer are normally-on devices. The formation of contacts on the AlGaN layer does not change the charge polarization in the heterostructure such that, if there was a 2DEG present before processing, it would remain there after formation of contacts on top of the AlGaN layer. A certain negative voltage, called threshold voltage, on the gate is required to deplete the 2DEG through capacitive coupling. By applying a negative voltage to the gate, the electron channel can be pinched off. This negative voltage is typically below a negative threshold voltage (Vth), typically between −4 V and −8 V. These transistors work in depletion-mode (D-mode) which means that the channel has to be depleted to switch off the transistor.
For certain applications, such as e.g. power switching or integrated logic, a negative-polarity gate voltage supply is not wanted; the gate control of power devices in e.g. power supplies should be made similar to that used for Si devices. Field-effect transistors (FET) with a threshold voltage Vth=0 V are normally-off devices. At zero gate voltage, no channel is present to conduct current. These transistors work in enhancement-mode (E-mode). E-mode transistors are attractive for normally-off power switches, for digital electronics applications, and for high efficiency RF applications.
To make a normally-off device, i.e. a device where no current can flow between source and drain contact when the gate is floating or grounded, the channel selectively under that gate contact can be interrupted while at the same time preserving an as high as possible 2DEG density in the other regions. A positive threshold voltage will then induce 2DEG under the gate contact, allowing current to flow between source and drain. Several methods have been reported to achieve such an E-mode transistor. For example, a reduction of the barrier thickness or a gate recess technology has been performed in order to decrease the gate to channel distance resulting in positive threshold voltages. Also, a self-aligned fluorine implantation prior to the gate deposition has been employed in order to locally deplete the bi-dimensional electron gas. More recently, E-Mode devices have been obtained by using hole injection from a p-type AlGaN material under the gate to the AlGaN/GaN heterojunction. However, all these methods result in poor device performances as compared to depletion mode devices, especially in terms of maximum current density.
In the E-Mode configuration, a metal insulator semiconductor high electron mobility transistor (MISHEMT) is preferred because of the possibility to overdrive the gate in the forward direction which enables to benefit from the full sheet carrier density. In the case of MISHEMTs, gate dielectrics have been used comprising SiO2, Si3N4 and other oxides with high dielectric constant such as Al2O3, HfO2 or Sc2O3 (high k dielectrics). However, in all cases, the interface between the semiconductor and the deposited oxide is difficult to control which prevent to benefit from the full potentiality of the MISHEMT configuration.
U.S. Pat. No. 5,929,467 describes a GaN-type field effect transistor with a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer in between. The channel layer is formed from n-type GaN. The insulating film is formed of AlN or AlGaN and increases the Schottky barrier height thereby obtaining a large input amplitude.
U.S. Pat. No. 6,989,556 describes a self-aligned enhancement mode metal-oxide compound semiconductor field-effect transistor including a gate insulating structure comprising a first oxide layer that includes a mixture of indium and gallium oxide compounds positioned directly on top of the compound semiconductor structure and a second insulating layer comprising either gallium, oxygen and rare earth elements or gallium, sulphur and rare earth elements positioned on top of the first layer.
WO 2007/041595 recites a III-nitride semiconductor device which includes a gate structure composed of, for example SiO2 or Si3N4 and a gate electrode.